Single Cycle MIPS CPU in VHDL

by Raivis Strogonovs In: Projects
mips32, vhdl, computer architecture 3 Comments
JUN 14 2013
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As the headline states single cycle MIPS32 processor implementation. I have implemented register file, instruction fetcher, Arithemtic Logic Unit (ALU), control unit and snychronous write/ asynchronous read memory. No pipelining though. This is a very simple implementation for learning purposes. Honestly for me this was one the most enjoyable lectures I had, I always wanted to learn how actually a CPU works. Conitnue reading to access the report!


 

Files:

Download: Report.docx (457.75K)

Download: Report.pdf (726.70K)

Download: MIPS32_project_files.rar (8.37M)

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