Single Cycle MIPS CPU in VHDL

As the headline states single cycle MIPS32 processor implementation. I have implemented register file, instruction fetcher, Arithemtic Logic Unit (ALU), control unit and snychronous write/ asynchronous read memory. No pipelining though. This is a very simple implementation for learning purposes. Honestly for me this was one the most enjoyable lectures I had, I always wanted to learn how actually a CPU works. Conitnue reading to access the report!

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